Bus trace tools are an integral part of validation and debug of integrated circuits and systems formed using such components. These tools (generally referred to herein as trace tools or logic analyzers (LA)) observe a bus or link and are able to interpret and capture data transmitted on the interconnect into instrument memory for display or analysis by debuggers. Training operations allow link agents and trace tools to establish synchronization, i.e., knowledge of where they are in a bit stream, to enable proper interpretation of a received bit stream.
In order to effectively debug rarely occurring problems, logic analyzers must be able to operate for long periods of time (e.g., weeks) without getting lost with regard to what is happening on the link. Lost here is used to indicate a condition where the logic analyzer can not make sense of what is on the link. This occurs when the logic analyzer loses synchronization or “framing” due to bit slip or add (the receiver erroneously loses or adds a bit to the received data stream). The nature of capture of certain interconnects such as serial links that operate at high speeds is such that there is inherently a non-zero bit error rate (BER). While small (typically on the order of 10−12 or less), this error rate is still high enough such that over a sufficient amount of time, errors will occur. For example, for both directions of a 16 lane, 8 gigabits per second (Gbs) link, an error would occur approximately once every 4 seconds at a 10−12 BER (though errors that result in bit slip or add and cause loss of LA synchronization are expected to be much less frequent). These errors occur in both the link itself and in the trace tool capture of the bus independent of errors occurring on the link. Current methods of recovering from such errors can be ineffective.